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| STPC(R) CONSUMER-S PC Compatible Embeded Microprocessor s s s s s s s s s s s s s s s POWERFUL x86 PROCESSOR 64-BIT 66MHz SDRAM UMA CONTROLLER -SUPPORTS 16Mbit SDRAMs (4MX4, 2MX8, 1MX16). VGA & SVGA CRT CONTROLLER 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT TV OUTPUT - 3-LINE FLICKER FILTER - CCIR 601/656 SCAN CONVERTER - NTSC / PAL COMPOSITE, RGB, S-VIDEO PCI MASTER / SLAVE CONTROLLER ISA MASTER / SLAVE CONTROLLER INTEGRATED PERIPHERAL CONTROLLER - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS OPTIONAL 16-BIT LOCAL BUS INTERFACE EIDE CONTROLLER IC INTERFACE POWER MANAGEMENT UNIT 3.45V OPERATION PBGA388 Figure 0-1. Logic Diagram Host x86 PCI m/s PCI Bus PMU ISA PCI IDE IPC ISA Bus LB Local Bus STPC CONSUMER-S OVERVIEW The STPC Consumer-S integrates a standard 5th generation x86 core, a Synchronous DRAM controller, a graphics subsystem, a video input port, video pipeline, and support logic including PCI, ISA, and IDE controllers to provide a single consumer orientated PC compatible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing the same memory array between the CPU main memory and the graphics and video frame buffers. The STPC Consumer-S is packaged in a 388 Plastic Ball Grid Array (PBGA). Video C Key Monitor SVGA CRTC K Key TVO Cursor Encoder GE VIP SDRAM TV Issue 1.1 - October 16, 2000 1/59 STPC CONSUMER-S OVERVIEW s s s s s s s X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back and write through capability. Parallel processing integral floating point unit, with automatic power down. Fully static design for dynamic clock control. Low power and system management modes. s s s s s s s s s CRT Controller Integrated 135MHz triple RAMDAC allowing for 1024 x 768 x 75Hz display. 8-, 16-, 24-bit pixels. Interlaced or non-interlaced output. Video Input port Accepts video inputs in CCIR 601 mode. Optional 2:1 decimator Stores captured video in off setting area of the onboard frame buffer. Video pass through to the onchip PAL/NTSC encoder for full screen video images. HSYNC and B/T generation or lock onto external video timing source. s s s s s s s s s s s s s s s s s s SDRAM Controller 64-bit data bus. Up to 66MHz SDRAM clock speed. Integrated system memory, graphic frame memory and video frame memory. Supports 2MB up to 128 MB memory. Supports 8MB, 16M, and 32MB DIMMS. Supports buffered, non buffered, and registered DIMMS. 4-line write buffers for CPU to DRAM and PCI to DRAM cycles. 4-line read prefetch buffers for PCI masters. Programmable latency Programmable timing for DRAM parameters. Supports -8, -10 memory parts Supports 1MB up to 8MB memory hole. 32-bit accesses not supported. Autoprecharge not supported. Power down not supported. FPM and EDO not supported. Supports 16M-bit full page mode SDRAMS's (1M x 16, 2M x 8 & 4M x 4) s s s s s s s Video Pipeline Two-tap interpolative horizontal filter. Two-tap interpolative vertical filter. Color space conversion. Programmable window size. Chroma and color keying for integrated video overlay. s s s s s s s s s s s s s s Graphics Controller 64-bit windows accelerator. Compatibility to VGA & SVGA standards. Hardware acceleration for text, bitblts, transparent blts and fills. Up to 64 x 64 bit graphics hardware cursor. Up to 4MB long linear frame buffer. 8-, 16-, and 24-bit pixels. s s s s TV Output Programmable two tap filter with gamma correction or three tap flicker filter. Progressive to interlaced scan converter. NTSC-M, PAL-M,PAL-B,D,G,H,I,PAL-N easy programmable video outputs. CCIR601 encoding with programmable color subcarrier frequencies. Line skip/insert capability Interlaced or non-interlaced operation mode. 625 lines/50Hz or 525 lines/60Hz 8 bit multiplexed CB-Y-CR digital input. CVBS and R,G,B simultaneous analog outputs through 10-bit DACs. Cross color reduction by specific trap filtering on luma within CVBS flow. Power down mode available on each DAC. 2/59 Issue 1.1 - October 16, 2000 STPC CONSUMER-S OVERVIEW s s s s s s s PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface. Up to 3 masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle to PCI. Support for burst read/write from PCI master. PCI clock is 1/3 or 1/2 Host clock . s s s s s s s s s s s s s s s s s s s s ISA master/slave controller Generates the ISA clock from either 14.318MHz oscillator clock or PCI clock Supports programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/ O cycles. Fast Gate A20 and Fast reset. Supports the single ROM that C, D, or E. blocks shares with F block BIOS ROM. Supports flash ROM. Supports ISA hidden refresh. Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI and Host bus. NSP compliant. Local Bus interface Multiplxed with ISA interface. Low latency bus 22-bit address bus. 16-bit data bus with word steering capability. Programmable timing (Host clock granularity) 2 Programmable Flash Chip Select. 4 Programmable I/O Chip Select. Supports 32-bit Flash burst. 2-level hardware key protection for Flash boot block protection. Supports 2 banks of 8MB flash devices with boot block shadowed to 0x000F0000. s s s s s s s s s s s s s s s s s s s Integrated Peripheral Controller 2X8237/AT compatible 7-channel DMA controller. 2X8259/AT compatible interrupt Controller. 16 interrupt inputs - ISA and PCI. Three 8254 compatible Timer/Counters. Co-processor error support logic. Supports external RTC. s s IDE Interface Supports PIO and Bus Master IDE Supports up to Mode 5 Timings Transfer Rates to 22 MBytes/sec Supports up to 4 IDE devices Concurrent channel operation (PIO & DMA modes) - 4 x 32-Bit Buffer FIFO per channel Support for PIO mode 3 & 4. Support for DMA mode 1 & 2. Bus Master with scatter/gather capability Multi-word DMA support for fast IDE drives Individual drive timing for all four IDE devices Supports both legacy & native IDE modes Supports hard drives larger than 528MB Support for CD-ROM and tape peripherals Backward compatibility with IDE (ATA-1). s s s s s s s s Power Management Four power saving modes: On, Doze, Standby, Suspend. Programmable system activity detector Supports SMM. Supports STOPCLK. Supports IO trap & restart. Independent peripheral time-out timer to monitor hard disk, serial & parallel ports. Supports RTC, interrupts and DMAs wake-up Issue 1.1 - October 16, 2000 3/59 GENERAL DESCRIPTION 1 GENERAL DESCRIPTION At the heart of the STPC Consumer-S is an advanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a 5th generation processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry standard PC chip set functions (Interrupt controller, DMA Controller, Interval timer and ISA bus). The STPC Consumer-S makes use of a tightly coupled Unified Memory Architecture (UMA), where the same memory array is used for CPU main memory and graphics frame-buffer. This means a reduction in total system memory for system performances that are equal to that of a comparable Frame Buffer and system memory based system, and generally much better, due to the higher memory bandwidth allowed by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional PCI bus. The 64-bit wide memory array provides the system with 528MB/s peak bandwidth. This allows for higher resolution screens and greater color depth. The `standard' PC chipset functions (DMA, interrupt controller, timers, power management logic) are integrated together with the x86 processor core; additional functions such as communications ports are accessed by the STPC ConsumerS via internal ISA bus. The PCI bus is the main data communication link to the STPC Consumer-S chip. The STPC Consumer-S translates appropriate host bus I/O and Memory cycles onto the PCI bus. It also supports generation of Configuration cycles on the PCI bus. The STPC Consumer-S, as a PCI bus agent (host bridge class), fully complies with PCI specification 2.1. The chip-set also implements the PCI mandatory header registers in Type 0 PCI configuration space for easy porting of PCI aware system BIOS. The device contains a PCI arbitration function for three external PCI devices. The STPC Consumer-S has two functionnal blocks sharing the same balls : The ISA / IPC / IDE block and the Local Bus / IDE block (see Table 2-1 & Table 2-4). Any board with the STPC Consumer-S should be built using only one of these two configurations. At reset, the configuration is done by `strap options' which initialises the STPC Consumer-S to the right settings. It is a set of pull-up or pull-down 4/59 resistors on the memory data bus, checked on reset, which auto-configure the STPC Consumer-S. GRAPHICS FUNCTIONS Graphics functions are controlled through the onchip SVGA controller and the monitor display is produced through the 2D graphics display engine. This Graphics Engine is tuned to work with the host CPU to provide a balanced graphics system with a low silicon area cost. It performs limited graphics drawing operations which include hardware acceleration of text, bitblts, transparent blts and fills. The results of these operations change the contents of the on-screen or off-screen Frame Buffer areas of DRAM memory. The Frame Buffer can occupy a space up to 4 Mbytes anywhere in the physical main memory and always starts from the bottom of the main physical memory. The graphics resolution supported is a maximum of 1280x1024 in 65536 colours and 1024x768 in true color at 75Hz refresh rate and is VGA and SVGA compatible. Horizontal timing fields are VGA compatible while the vertical fields are extended by one bit to accommodate above display resolution. VIDEO FUNCTIONS The STPC Consumer-S provides several additional functions to handle MPEG or similar video streams. The Video Input Port accepts an encoded digital video stream in one of a number of industry standard formats, decodes it, optionally decimates it, and deposits it into an off screen area of the Frame Buffer. An interrupt request can be generated when an entire field or frame has been captured. The video output pipeline incorporates a video-scaler and color space converter function and provisions in the CRT controller to display a video window. While repainting the screen the CRT controller fetches both the video as well as the normal non-video Frame Buffer in two separate internal FIFOs. The video stream can be color-space converted (optionally) and smooth scaled. Smooth interpolative scaling in both horizontal and vertical direction are implemented. Color and Chroma key functions are also implemented to allow mixing video stream with non-video Frame Buffer. The video output passes directly to the RAMDAC for monitor output or through another optional color space converter (RGB to 4:2:2 YCrCb) to the programmable anti-flicker filter. The flicker filter is Issue 1.1 - October 16, 2000 GENERAL DESCRIPTION configured as either a two line filter with gamma correction (primarily designed for DOS type text) or a 3 line flicker filter (primarily designed for Windows type displays). The flicker filter is optional and can be software disabled for use with large screen area's of video. The Video output pipeline of the STPC ConsumerS interfaces directly to the internal digital TV encoder. It takes a 24 bit RGB non-interlaced pixel stream and converts to a multiplexed 4:2:2 YCrCb 8 bit output stream, the logic includes a progressive to interlaced scan converter and logic to insert appropriate CCIR656 timing reference codes into the output stream. It facilitates the high quality display of VGA or full screen video streams received via the Video input port to standard NTSC or PAL televisions. The digital PAL/NTSC encoder outputs interlaced or non-interlaced video in PAL-B,D,G,H,I PAL-N, PAL-M or NTSC-M standards and "NTSC- 4.43" is also possible. The four frame (for PAL) or 2 frame (for NTSC) burst sequences are internally generated, subcarrier generation being performed numerically with CKREF as reference. Rise and fall times of synchronisation tips and burst envelope are internally controlled according to the relevant ITU-R and SMPTE recommendations. Video output signals are directed to four analog output pins through internal D/A converters giving, simultaneous R,G,B and composite CVBS and SVHS outputs. MEMORY CONTROLLER The STPC handles the memory data (DATA) bus directly, controlling from 2 to 128 MBytes. The SDRAM controller supports accesses to the Memory Banks to/from the CPU (via the host), from the VIP, to/from the CRTC, to the VIDEO & to/from the GE. (Banks 0 to 3) which can be populated with either single or double sided 72-bit (4 bit parity) DIMMs. Parity is not supported. The SDRAM controller only supports 64 bit wide Memory Banks. Four Memory Banks (if DIMMS are used; Single sided or two double-sided DIMMs) are supported in the following configurations (see Table 1-1): Table 1-1. Supported Memory Configs Memory Bank size 1Mx64 2Mx64 4Mx64 Number 4 8 16 Organisation 1Mx16 2Mx8 4Mx4 16Mbit Device size The SDRAM Controller supports buffered or unbuffered SDRAM but not EDO or FPM modes. SDRAMs must support Full Page Mode Type access. The STPC Memory Controller provides various programmable SDRAM parameters to allow the SDRAM interface to be optimized for different processor bus speeds SDRAM speed grades and CAS Latency. IDE INTERFACE An industry standard EIDE (ATA 2) controller is built into the STPC Consumer-S. The IDE port is capable of supporting a total of four devices. POWER MANAGEMENT The STPC Consumer-S core is compliant with the Advanced Power Management (APM) specification to provide a standard method by which the BIOS can control the power used by personal computers. The Power Management Unit module (PMU) controls the power consumption providing a comprehensive set of features that control the power usage and supports compliance with the United States Environmental Protection Agency's Energy Star Computer Program. The PMU provides following hardware structures to assist the software in managing the power consumption by the system. - System Activity Detection. - Three power down timers. - Doze timer for detecting lack of system activity for short durations. - Stand-by timer for detecting lack of system activity for medium durations - Suspend timer for detecting lack of system activity for long durations. - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by Issue 1.1 - October 16, 2000 5/59 GENERAL DESCRIPTION state. - Peripheral activity detection. - Peripheral timer for detecting lack of peripheral activity - SUSP# modulation to adjust the system performance in various power down states of the system including full power on state. - Power control outputs to disable power from different planes of the board. Lack of system activity for progressively longer period of times is detected by the three power down timers. These timers can generate SMI interrupts to CPU so that the SMM software can put the system in decreasing states of power consumption. Alternatively, system activity in a power down state can generate SMI interrupt to allow the software to bring the system back up to full power on state. The chip-set supports up to three power down states: Doze state, Stand-by state and Suspend mode. These correspond to decreasing levels of power savings. POWER DOWN Power down puts the STPC Consumer-S into suspend mode. The processor completes execution of the current instruction, any pending decoded instructions and associated bus cycles. During the suspend mode, internal clocks are stopped. Removing power down, the processor resumes instruction fetching and begins execution in the instruction stream at the point it had stopped. Because of the static nature of the core, no internal data is lost. 6/59 Issue 1.1 - October 16, 2000 GENERAL DESCRIPTION Figure 1-1. .Functionnal description. Host I/F x86 Core PCI BUS PMU watchdog PCI m/s IPC 82C206 ISA m/s PCI m/s IDE I/F ISA Bus Local Bus I/F Local Bus Video Pipeline - Pixel formating - Scaler - Colour Space CVT Colour Key Chroma Key LUT Monitor TVO - CSC - FF - CCIR NTSC/PAL Encoder SVGA CRTC HW Cursor GE VIP TV CCIR Input SDRAM I/F Issue 1.1 - October 16, 2000 7/59 GENERAL DESCRIPTION Figure 1-2. Typical Application Super I/O RTC Keyboard / Mouse Serial Ports Parallel Port Floppy Flash ISA DMUX MUX 2x EIDE IRQ MUX Monitor SVGA DMA.REQ TV S-VHS RGB PAL NTSC STPC Consumer-S DMA.ACK DMUX Video CCIR601 CCIR656 PCI 4x 16-bit SDRAMs 8/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION 2 PIN DESCRIPTION 2.1 INTRODUCTION The STPC Consumer-S integrates most of the functionalities of the PC architecture. As a result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Consumer-S. This offers improved performance due to the tight coupling of the processor core and these peripherals. As a result many of the external pin connections are made directly to the on-chip peripheral functions. Figure 2-1 shows the STPC Consumer-S external interfaces. It defines the main busses and their function. Table 2-1 describes the physical implementation listing signals type and their functionality. Table 2-2 provides a full pin listing and description of pins. Table 2-5 provides a full listing of pin locations of the STPC Consumer-S package by physical connection. Table 2-1. Signal Description Group name System Clocks & Resets (SYS) SDRAM Controler PCI interface ISA Interface IDE Controller Local Bus Video Input TV Output VGA Monitor interface Grounds VDD Miscelaneous Unconnected Total Pin Count Qty 7 95 56 79 34 49 89 9 10 8 74 29 4 7 388 Note: Several interface pins are multiplexed with other functions, refer to Table 2-3 and Table 2-4 for further details Figure 2-1. STPC Consumer-S External Interfaces x86 STPC CONSUMER-S PCI SDRAM VGA VIP TV SYS ISA/IDE/LB 96 8 9 10 56 7 89 Issue 1.1 - October 16, 2000 9/59 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name BASIC CLOCKS AND RESETS SYSRSTI#2 SYSRSTO#2 XTALI XTALO HCLK2 DEV_CLK DCLK 2 VDD_xxx_PLL1 MEMORY INTERFACE MCLKI MCLKO CS#[3:0] BA[0] MA[10:0] MD[63:0]2 RAS#[1:0] CAS#[1:0] MWE# DQM[7:0] PCI INTERFACE PCI_CLKI2 PCI_CLKO AD[31:0]2 CBE#[3:0]2 FRAME#2 IRDY#2 TRDY#2 LOCK#2 DEVSEL#2 STOP#2 PAR2 SERR#2 PCI_REQ#[2:0]2 PCI_GNT#[2:0]2 PCI_INT[3:0]2 VDD5 Dir I O I I/O I/O O I/O Description System Power Good Input System Reset Output 14.3MHz Crystal Input 14.3MHz Crystal Output - External Oscillator Input Host Clock (Test) 24MHz Peripheral Clock (floppy drive) 27-135MHz Graphics Dot Clock Power Supply for PLL Clocks Qty 1 1 1 1 1 1 1 I O O O O I/O O O O O Memory Clock Input Memory Clock Output Memory Bank Chip Select Memory Row & Column Address/Bank Address Memory Row & Column Address Memory Data Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask 1 1 4 1 11 64 2 2 1 8 I O I/O I/O I/O I/O I/O I I/O I/O I/O O I O I I 33MHz PCI Input Clock 33MHz PCI Output Clock (from internal PLL) PCI Address / Data Bus Commands / Byte Enables Cycle Frame Initiator Ready Target Ready PCI Lock Device Select Stop Transaction Parity Signal Transactions System Error PCI Request PCI Grant PCI Interrupt Request 5V Power Supply for PCI ESD protection 1 1 32 4 1 1 1 1 1 1 1 1 3 3 4 4 ISA CONTROL ISA_CLK2 O ISA Clock Output - Multiplexer Select Line For IPC 1 ISA_CLK2X2 O ISA Clock x2 Output - Multiplexer Select Line For IPC 1 OSC14M 2 O ISA bus synchronisation clock 1 LA[23:17]2 O Unlatched Address 7 Note1; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply. Note2; Denotes that the pin is V5T (see Section 4 ) Note 3; see Table 2-5 for the detail of individual V5T signals 10/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name SA[19:0] SD[15:0]2 ALE2 MEMR#2, MEMW#2 SMEMR#2, SMEMW#2 IOR#2, IOW#2 MCS16# 2, IOCS16#2 BHE#2 ZWS#2 REF#2 MASTER#2 AEN2 IOCHCK#2 IOCHRDY2 ISAOE#2 GPIOCS#2 IRQ_MUX[3:0]2 DREQ_MUX[1:0]2 DACK_ENC[2:0]2 TC2 RTCAS#2 RMRTCCS#2 KBCS#2 RTCRW#2 RTCDS#2 LOCAL BUS PA[21:0] PD[15:0] PRD1#,PRD0# PWR1#,PWR0# PRDY# FCS1#, FCS0# IOCS#[3:0] Dir I/O I/O O I/O O I/O I O I O I O I I/O O I/O I I O O O I/O I/O I/O I/O Description Latched Address Data Bus Address Latch Enable Memory Read and Memory Write System Memory Read and Memory Write I/O Read and Write Memory/IO Chip Select16 System Bus High Enable Zero Wait State Refresh Cycle. Add On Card Owns Bus Address Enable I/O Channel Check. I/O Channel Ready (ISA) - Busy/Ready (IDE) ISA/IDE Selection General Purpose Chip Select Time-Multiplexed Interrupt Request Time-Multiplexed DMA Request Encoded DMA Acknowledge ISA Terminal Count Real Time Clock Address Strobe ROM/RTC Chip Select Keyboard Chip Select RTC Read/Write RTC Data Strobe Qty 20 16 1 2 2 2 2 1 1 1 1 1 1 1 1 1 4 2 3 1 1 1 1 1 1 O I/O O O I O O Address Bus Data Bus Peripheral Read Control Peripheral Write Control Data Ready Flash Chip Select I/O Chip Select 22 16 2 2 1 2 4 IDE CONTROL DA[2:0] O Address Bus 3 DD[15:0] I/O Data Bus 16 PCS3#,PCS1#,SCS3#,SCS1# O Primary & Secondary Chip Selects 4 DIORDY O Data I/O Ready 1 PIRQ2, SIRQ2 I Primary & Secondary Interrupt Request 2 PDRQ2, SDRQ2 I Primary & Secondary DMA Request 2 PDACK#2, SDACK#2 O Primary & Secondary DMA Acknowledge 2 PDIOR#2, SDIOR#2 O Primary & Secondary I/O Channel Read 2 PDIOW#2, SDIOW#2 O Primary & Secondary I/O Channel Write 2 Note1; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply. Note2; Denotes that the pin is V5T (see Section 4 ) Note 3; see Table 2-5 for the detail of individual V5T signals Issue 1.1 - October 16, 2000 11/59 PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name MONITOR INTERFACE RED, GREEN, BLUE VSYNC2 HSYNC2 VREF_DAC RSET COMP VIDEO INPUT VCLK2 VIN[7:0]2 ANALOG TV OUTPUT RED_TV2, GREEN_TV2, BLUE_TV2 Dir Description Qty O O O I I I I I Analog Red, Green, Blue Vertical Sync Horizontal Sync DAC Voltage reference Resistor Set Compensation 27-33MHz Video Input Port Clock CCIR 601 or 656 YUV Video Data Input 3 1 1 1 1 1 1 8 CVBS2 IREF1_TV VREF1_TV IREF2_TV2 VREF2_TV2 VSSA_TV VDDA_TV VCS2 ODD_EVEN2 O O I I I I I I I/O I/O Analog RGB or S-VHS outputs Analog video composite output Reference current of 9bit DAC for CVBS Reference voltage of 9bit DAC for CVBS Reference current of 8bit DAC for R,G,B Reference voltage of 8bit DAC for R,G,B Analog Vss for DAC Analog Vdd for DAC Composite Synch or Horizontal line SYNC output Frame Synchronisation 3 1 1 1 1 1 1 1 1 1 MISCELLANEOUS SPKRD2 O Speaker Device Output 1 SCL2 I/O IC Interface - Clock / Can be used for VGA DDC[1] signal 1 SDA2 I/O IC Interface - Data / Can be used for VGA DDC[0] signal 1 SCAN_ENABLE2 I Reserved (Test pin) 1 Note1; These pins must be connected to the 2.5Vpower supply. They must not be connected to the 3.45V supply. Note2; Denotes that the pin is V5T (see Section 4 ) Note 3; see Table 2-5 for the detail of individual V5T signals 12/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION 2.2 SIGNAL DESCRIPTIONS 2.2.1 BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply's power good signal. This input is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of this signal. SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output. XTALI 14.3MHz Crystal Input XTALO 14.3MHz Crystal Output. These pins are connected to the 14.318 MHz crystal to provide the reference clock for the internal frequency synthesizer to generate all the other clocks. A 14.318 MHz Series Cut Crystal should be connected between these two pins. Balance capacitors of 15 pF should also be added. In the event of an external quarzt oscillator providing the master clock signal to the STPC Consumer-S device, the TTL signal should be provided on XTALO. HCLK Host Clock. This clock supplies the CPU and the host related blocks. This clock can e doubled inside the CPU and is intended to operate in the range of 25 to 100 MHz. This clock in generated internally from a PLL but can be driven directly from the external system. DEV_CLK 24MHz Peripheral Clock. This 24MHZ signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. DCLK 135MHz Dot Clock. This is the Dot clock, which drives graphics display cycles. Its frequency can go from 8MHz (using internal PLL) up to 135 MHz, and it is required to have a worst case duty cycle of 60-40. This signal is either driven by the internal pll (VGA) or an external 27MHz oscillator (when the composite video output is enabled). The direction can be controlled by a strap option or an internal register bit. 2.2.2 MEMORY INTERFACE MCLKI Memory Clock Input. This clock is driving the SDRAM controller, the graphics engine and display controller. This input should be a buffered version of the MCLKO signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the Memory Banks. MCLKO Memory Clock Output. This clock drives the Memory Banks on board and is generated from an internal PLL.The default value is 80MHz. CS#[3:0] Chip Select These signals are used to disable or enable device operation by masking or enabling all SDRAM inputs except MCLK, CKE, and DQM. BA[0] Memory Bank Address. MA[10:0] Memory Address. Multiplexed row and column address lines. MD[63:0] Memory Data. This is the 64-bit memory data bus. MD[40-0] are read by the device strap option registers during rising edge of SYSRSTI#. RAS#[1:0] Row Address Strobe. These signals enable row access and precharge. Row address is latched on rising edge of MCLK when RAS# is low. CAS#[1:0] Column Address Strobe. These signals enable column access. Column address is latched on rising edge of MCLK when CAS# is low. MWE# Write Enable. Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). DQM#[7:0] Data Mask. Makes data output Hi-Z after the clock and masks the SDRAM outputs. It blocks SDRAM data input when DQM active. 2.2.3 PCI INTERFACE PCI_CLKI 33MHz PCI Input Clock. This signal is the PCI bus clock input and should be driven from the PCI_CLKO pin. PCI_CLKO 33MHz PCI Output Clock. This is the master PCI bus clock output. AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. Signals AD[12:11] for internal use only. Not to be used for External PCI devices. Issue 1.1 - October 16, 2000 13/59 PIN DESCRIPTION CBE#[3:0] Bus Commands/Byte Enables. These are the multiplexed command and byte enable signals of the PCI bus. During the address phase they define the command and during the data phase they carry the byte enable information. These pins are inputs when a PCI master other than the STPC Consumer-S owns the bus and outputs when the STPC Consumer-S owns the bus. FRAME# Cycle Frame. This is the frame signal of the PCI bus. It is an input when a PCI master owns the bus and is an output when STPC Consumer-S owns the PCI bus. IRDY# Initiator Ready. This is the initiator ready signal of the PCI bus. It is used as an output when the STPC Consumer-S initiates a bus cycle on the PCI bus. It is used as an input during the PCI cycles targeted to the STPC Consumer-S to determine when the current PCI master is ready to complete the current transaction. TRDY# Target Ready. This is the target ready signal of the PCI bus. It is driven as an output when the STPC Consumer-S is the target of the current bus transaction. It is used as an input when STPC Consumer-S initiates a cycle on the PCI bus. LOCK# PCI Lock. This is the lock signal of the PCI bus and is used to implement the exclusive bus operations when acting as a PCI target agent. DEVSEL# I/O Device Select. This signal is used as an input when the STPC Consumer-S initiates a bus cycle on the PCI bus to determine if a PCI slave device has decoded itself to be the target of the current transaction. It is asserted as an output either when the STPC Consumer-S is the target of the current PCI transaction or when no other device asserts DEVSEL# prior to the subtractive decode phase of the current PCI transaction. STOP# Stop Transaction. Stop is used to implement the disconnect, retry and abort protocol of the PCI bus. It is used as an input for the bus cycles initiated by the STPC Consumer-S and is used as an output when a PCI master cycle is targeted to the STPC Consumer-S. PAR Parity Signal Transactions. This is the parity signal of the PCI bus. This signal is used to guarantee even parity across AD[31:0], CBE#[3:0], and PAR. This signal is driven by the master during the address phase and data phase of write transactions. It is driven by the target during data phase of read transactions. (Its assertion is identical to that of the AD bus delayed by one PCI clock cycle) SERR# System Error. This is the system error signal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Consumer-S initiated PCI transaction. Its assertion by either the STPC Consumer-S or by another PCI bus agent will trigger the assertion of NMI to the host CPU. This is an open drain output. PCI_REQ#[2:0] PCI Request. This pin are the three external PCI master request pins. They indicates to the PCI arbiter that the external agents desire use of the bus. PCI_GNT#[2:0] PCI Grant. These pins indicate that the PCI bus has been granted to the master requesting it on its PCI_REQ#. PCI_INT[3:0] PCI Interrupt Request. These are the PCI bus interrupt signals. VDD5 5V Power Supply. These power pins are necessary for 5V ESD protection. In case the PCI bus is used in 3.45V only, these pins can be connected to 3.45V. 2.2.4 ISA INTERFACE ISA_CLK, ISA_CLKX2 ISA Clock x1, x2. These pins generate the Clock signal for the ISA bus and a Doubled Clock signal. They are also used as the multiplexor control lines for the Interrupt Controller Interrupt input lines. ISA_CLK is generated from either PCICLK/4 or OSC14M/ 2. OSC14M ISA bus synchronisation clock Output. This is the buffered 14.318 Mhz clock for the ISA bus. LA[23:17] Unlatched Address. When the ISA bus is active, these pins are ISA Bus unlatched address for 16-bit devices. When ISA bus is accessed by any cycle initiated from PCI bus, these pins are in output mode. When an ISA bus master owns the bus, these pins are in input mode. SA[19:0] ISA Address Bus. System address bus of ISA on 8-bit slot. These pins are used as an input when an ISA bus master owns the bus and are outputs at all other times. SD[15:0] I/O Data Bus. These pins are the external databus to the ISA bus. ALE Address Latch Enable. This is the address latch enable output of the ISA bus and is asserted by the STPC Consumer-S to indicate that LA2317, SA19-0, AEN and SBHE# signals are valid. The ALE is driven high during refresh, DMA mas- 14/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION ter or an ISA master cycles by the STPC Consumer-S. ALE is driven low after reset. MEMR# Memory Read. This is the memory read command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. The MEMR# signal is active during refresh. MEMW# Memory Write. This is the memory write command signal of the ISA bus. It is used as an input when an ISA master owns the bus and is an output at all other times. SMEMR# System Memory Read. The STPC Consumer-S generates SMEMR# signal of the ISA bus only when the address is below one megabyte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC Consumer-S generates SMEMW# signal of the ISA bus only when the address is below one megabyte. IOR# I/O Read. This is the IO read command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. IOW# I/O Write. This is the IO write command signal of the ISA bus. It is an input when an ISA master owns the bus and is an output at all other times. MCS16# Memory Chip Select16. This is the decode of LA23-17 address pins of the ISA address bus without any qualification of the command signal lines. MCS16# is always an input. The STPC Consumer-S ignores this signal during IO and refresh cycles. IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins of the ISA address bus without any qualification of the command signals. The STPC Consumer-S does not drive IOCS16# (similar to PC-AT design). An ISA master access to an internal register of the STPC Consumer-S is executed as an extended 8-bit IO cycle. BHE# System Bus High Enable. This signal, when asserted, indicates that a data byte is being transferred on SD15-8 lines. It is used as an input when an ISA master owns the bus and is an output at all other times. ZWS# Zero Wait State. This signal, when asserted by addressed device, indicates that current cycle can be shortened. REF# Refresh Cycle. This is the refresh command signal of the ISA bus. It is driven as an output when the STPC Consumer-S performs a refresh cycle on the ISA bus. It is used as an input when an ISA master owns the bus and is used to trigger a refresh cycle. The STPC Consumer-S performs a pseudo hidden refresh. It requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. The host bus is then relinquished while the refresh cycle continues on the ISA bus. MASTER# Add On Card Owns Bus. This signal is active when an ISA device has been granted bus ownership. AEN Address Enable. Address Enable is enabled when the DMA controller is the bus owner to indicate that a DMA transfer will occur. The enabling of the signal indicates to IO devices to ignore the IOR#/IOW# signal during DMA transfers. IOCHCK# IO Channel Check. IO Channel Check is enabled by any ISA device to signal an error condition that can not be corrected. NMI signal becomes active upon seeing IOCHCK# active if the corresponding bit in Port B is enabled. IOCHRDY Channel Ready. IOCHRDY is the IO channel ready signal of the ISA bus and is driven as an output in response to an ISA master cycle targeted to the host bus or an internal register of the STPC Consumer-S. The STPC Consumer-S monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with the STPC ConsumerS since the access to the system memory can be considerably delayed due UMA architecture. ISAOE# Bidirectional OE Control. This signal controls the OE signal of the external transceiver that connects the IDE DD bus and ISA SA bus. GPIOCS# I/O General Purpose Chip Select. This output signal is used by the external latch on ISA bus to latch the data on the SD[7:0] bus. The latch can be use by PMU unit to control the external peripheral devices or any other desired function. IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They have to be encoded before connection to the STPC Consumer-S using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connected to the RTC, is inverted before being sent to the Issue 1.1 - October 16, 2000 15/59 PIN DESCRIPTION interrupt controller, so that it may be connected directly to the IRQ pin of the RTC. DREQ_MUX[1:0] ISA Bus Multiplexed DMA Request. These are the ISA bus DMA request signals. They are to be encoded before connection to the STPC Consumer-S using ISACLK and ISACLKX2 as the input selection strobes. DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Consumer-S before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the byte count expires. 2.2.5 X-Bus Interface pins 2.2.7 IDE INTERFACE RTCAS# Real time clock address strobe. This signal is asserted for any I/O write to port 70H. RMRTCCS# ROM/Real Time clock chip select. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During a IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR or IOW# signals to properly access the real time clock. KBCS# Keyboard Chip Select. This signal is asserted if a keyboard access is decoded during a I/ O cycle. RTCRW# Real Time Clock RW. This pin is a multifunction pin. When ISAOE# is active, this signal is used as RTCRW#. This signal is asserted for any I/O write to port 71H. RTCDS# Real Time Clock DS. This pin is a multifunction pin. When ISAOE# is active, this signal is used as RTCDS. This signal is asserted for any I/ O read to port 71H. Note: RMRTCCS#, KBCS#, RTCRW# and RTCDS# signals must be ORed externally with ISAOE# and then connected to the external device. An LS244 or equivalent function can be used if OE# is connected to ISAOE# and the output is provided with a weak pull-up resistor as shown in Figure 2-2. 2.2.6 LOCAL BUS PA[21:0] Address Bus Output. 16/59 PD[15:0] Data Bus. This is the 16-bit data bus. D[7:0] is the LSB and PD[15:8] is the MSB. PRD#[1:0] Read Control output. PRD0# is used to read the LSB and PRD1# to read the MSB. PWR#[1:0] Write Control output. PWR0# is used to write the LSB and PWR1# to write the MSB. PRDY# Data Ready input. This signal is used to create wait states on the bus. When HIGH it completes the cycle without any wait state added. FCS#[1:0] Flash Chip Select output. These are the Programmable Chip Select signals for up to 2 banks of Flash memory. IOCS#[3:0] I/O Chip Select output. These are the Programmable Chip Select signals for up to 4 external I/O devices. DA[2:0] Address. These signals are connected to DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals are to be masked during ISA bus cycles, they can be externally ORed with ISAOE# before being connected to the IDE devices. DD[15:0] Databus. When the IDE bus is active, they serve as IDE signals DD[15:0]. IDE devices are connected to SA[19:8] directly and ISA bus is connected to these pins through two LS245 transceivers as described in Figure 2-2. PCS1#, PCS3# Primary Chip Select. These signals are used as the active high primary master & slave IDE chip select signals. These signals must be externally ANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. SCS1#, SCS3# Secondary Chip Select. These signals are used as the active high secondary master & slave IDE chip select signals. These signals must be externally ANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. DIORDY Busy/Ready. This pin serves as IDE signal DIORDY. PIRQ Primary Interrupt Request. SIRQ Secondary Interrupt Request. Interrupt request from IDE channels. Issue 1.1 - October 16, 2000 PIN DESCRIPTION PDRQ Primary DMA Request. SDRQ Secondary DMA Request. DMA request from IDE channels. PDACK# Primary DMA Acknowledge. SDACK# Secondary DMA Acknowledge. DMA acknowledge to IDE channels. PDIOR#, PDIOW# Primary I/O Read & Write. SDIOR#, SDIOW# Secondary I/O Read & Write. Primary & Secondary channel read & write. 2.2.8 Monitor Interface RED, GREEN, BLUE RGB Video Outputs. These are the 3 analog color outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. An external voltage reference is connected to this pin to bias the DAC. RSET Resistor Current Set. This reference current input to the RAMDAC is used to set the fullscale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and VDD to damp oscillations. 2.2.9 VIDEO INPUT VCLK Pixel Clock Input.This signal is used to synchronise data being transfered from an external video device to either the frame buffer, or alternatively out the TV output in bypass mode. This pin can be sourced from STPC if no external VCLK is detected, or can be input from an external video clock source. VIN[7:0] YUV Video Data Input CCIR 601 or 656. Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus typically carries a stream of Cb,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. 2.2.10 TV OUTPUT RED_TV / C_TV Analog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Chrominance Output. GREEN_TV / Y_TV Analog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Luminance Output. BLUE_TV / CVBS Analog video outputs synchronized with CVBS. This output is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is a second composite output. CVBS Analog video composite output (luminance/ chrominance). CVBS is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. IREF1_TV Ref. current for CVBS 10-bit DAC. IREF2_TV Reference current for RGB 9-bit DAC. VREF1_TV Ref. voltage for CVBS 10-bit DAC. VREF2_TV Reference voltage for RGB 9-bit DAC. VSSA_TV Analog VSS for DACs. VDDA_TV Analog VDD for DACs. VCS Line synchronisation Output. This pin is an input in ODDEV+HSYNC or VSYNC + HSYNC or VSYNC slave modes and an output in all other modes (master/slave) ODD_EVEN Frame Synchronisation Ourput. This pin supports the Frame synchronisation signal. It is an input in slave modes, except when sync is extracted from YCrCbdata, and an output in master mode and when sync is extracted from YCrCb data The signal is synchronous to rising edge of DCLK. The default polarity for this pin is: - odd (not-top) field : LOW level - even (bottom) field : HIGH level Issue 1.1 - October 16, 2000 17/59 PIN DESCRIPTION 2.2.11 MISCELLANEOUS SPKRD Speaker Drive. This the output to the speaker and is AND of the counter 2 output with bit 1 of Port 61, and drives an external speaker driver. This output should be connected to 7407 type high voltage driver. SCL, SDA IC Interface. These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I2C electrical specifications, they have open-collector output drivers which are internally connected to VDD through pull-up resistors. They can be used for the DDC1 (SCL) and DDC0 (SDA) lines of the VGA interface. SCAN_ENABLE Reserved. Must be connected to ground. 18/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION Table 2-3. ISA / IDE dynamic multiplexing . ISA BUS (ISAOE# = 0) RMRTCCS# KBCS# RTCRW# RTCDS# SA[19:8] LA[23] LA[22] SA[21] SA[20] LA[19:17] IOCHRDY IDE (ISAOE# = 1) DD[15] DD[14] DD[13] DD[12] DD[11:0] SCS3# SCS1# PCS3# PCS1# DA[2:0] DIORDY Table 2-4. ISA / Local Bus pin sharing . ISA / IPC SD[15:0] DREQ_MUX[1:0] SMEMR# MEMW# BHE# AEN ALE MEMR# IOR# IOW# REF# IOCHCK# GPIOCS# ZWS# SA[7:4] TC, DACK_ENC[2:0] SA[3] ISAOE#,SA[2:0] DEV_CLK, RTCAS# IOCS16#, MASTER# SMEMW#, MCS16# ISACLK, ISA_CLK2X LOCAL BUS PD[15:0] PA[21:20] PA[19] PA[18] PA[17] PA[16] PA[15] PA[14] PA[13] PA[12] PA[11] PA[10] PA[9] PA[8] PA[7:4] PA[3:0] PRDY IOCS#[3:0] FCS#[1:0] PRD#[1:0] PWR#[1:0] Figure 2-2. Typical ISA/IDE Demultiplexing 74LS245 STPC bus / DD[15:0] MASTER# ISAOE# A DIR OE B RMRTCCS# KBCS# RTCRW# RTCDS SA[19:8] PCS1# LA[22] LA[23] PCS3# LA[22] SCS1# LA[23] SCS3# Issue 1.1 - October 16, 2000 19/59 PIN DESCRIPTION Table 2-5. Pinout. Pin # AF3 AE4 A3 C4 G23 H24 AD11 AF15 AB23 AE16 AD15 AF16 AE17 AD16 AF17 AE18 AD17 AF18 AE19 AE20 AC19 AF22 AD21 AE24 AD23 AF23 AD22 AE21 AC20 AF20 AD19 AF21 AD20 AE22 AE23 AF19 AD18 AC22 R1 T2 R3 T1 R4 U2 T3 U1 U4 V2 Pin name SYSRSTI# SYSRSTO# XTALI XTALO HCLK DEV_CLK DCLK MCLKI MCLKO MA[0] MA[1] MA[2] MA[3] MA[4] MA[5] MA[6] MA[7] MA[8] MA[9] MA[10] BA[0] CS#[0] CS#[1] CS#[2] CS#[3] RAS#[0] RAS#[1] CAS#[0] CAS#[1] DQM#[0] DQM#[1] DQM#[2] DQM#[3] DQM#[4] DQM#[5] DQM#[6] DQM#[7] MWE# MD[0] MD[1] MD[2] MD[3] MD[4] MD[5] MD[6] MD[7] MD[8] MD[9] Pin # U3 V1 W2 V3 Y2 W4 Y1 W3 AA2 Y4 AA1 Y3 AB2 AB1 AA3 AB4 AC1 AB3 AD2 AC3 AD1 AF2 AF24 AE26 AD25 AD26 AC25 AC24 AC26 AB25 AB24 AB26 AA25 Y23 AA24 AA26 Y25 Y26 Y24 W25 V23 W26 W24 V25 V26 U25 V24 U26 U23 Pin name MD[10] MD[11] MD[12] MD[13] MD[14] MD[15] MD[16] MD[17] MD[18] MD[19] MD[20] MD[21] MD[22] MD[23] MD[24] MD[25] MD[26] MD[27] MD[28] MD[29] MD[30] MD[31] MD[32] MD[33] MD[34] MD[35] MD[36] MD[37] MD[38] MD[39] MD[40] MD[41] MD[42] MD[43] MD[44] MD[45] MD[46] MD[47] MD[48] MD[49] MD[50] MD[51] MD[52] MD[53] MD[54] MD[55] MD[56] MD[57] MD[58] Pin # T25 U24 T26 R25 R26 F24 D25 B20 C20 B19 A19 C19 B18 A18 B17 C18 A17 D17 B16 C17 B15 A15 C16 B14 D15 A14 B13 D13 A13 C14 B12 C13 A12 C12 A11 D12 B10 C11 A10 D10 C10 A9 B8 A8 B7 D8 A7 C8 B6 Pin name MD[59] MD[60] MD[61] MD[62] MD[63] PCI_CLKI PCI_CLKO AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] CBE[0] CBE[1] CBE[2] CBE[3] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR 20/59 Issue 1.1 - October 16, 2000 PIN DESCRIPTION Pin # D7 A6 D20 C21 A21 C22 A22 B21 A5 C6 B4 D5 F2 G4 F3 F1 G2 G1 H2 J4 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 L1 M2 M1 L3 N2 M4 M3 P2 P4 K25 L24 K26 K23 J25 K24 J26 H25 H26 Pin name SERR# LOCK# PCI_REQ#[0] PCI_REQ#[1] PCI_REQ#[2] PCI_GNT#[0] PCI_GNT#[1] PCI_GNT#[2] PCI_INT[0] PCI_INT[1] PCI_INT[2] PCI_INT[3] LA[17]/DA[0] LA[18]/DA[1] LA[19]/DA[2] LA[20]/PCS1# LA[21]/PCS3# LA[22]/SCS1# LA[23]/SCS3# SA[0]2 SA[1]2 SA[2]2 SA[3]2 SA[4]2 SA[5]2 SA[6]2 SA[7]2 SA[8]2 SA[9]2 SA[10]2 SA[11]2 SA[12]2 SA[13]2 SA[14]2 SA[15]2 SA[16]2 SA[17]2 SA[18]2 SA[19]2 SD[0] SD[1] SD[2] SD[3] SD[4] SD[5] SD[6] SD[7] SD[8] Pin # J24 G25 H23 D24 C26 A25 B24 AD4 AF4 C9 P25 AE8 R23 P26 R24 N25 N23 N26 P24 N24 M26 M25 L25 M24 L26 T24 M23 A4 P3 R2 P1 AE3 E23 D26 E24 C25 A24 B23 C23 A23 B22 D22 N3 B1 C2 C1 D2 D3 Pin name SD[9] SD[10] SD[11] SD[12] SD[13] SD[14] SD[15] ISA_CLK ISA_CLK2X OSC14M ALE ZWS# BHE# MEMR# MEMW# SMEMR# SMEMW# IOR# IOW# MCS16# IOCS16# MASTER# REF# AEN IOCHCK# IOCHRDY ISAOE# RTCAS# RTCDS# RTCRW# RMRTCCS# GPIOCS# IRQ_MUX[0] IRQ_MUX[1] IRQ_MUX[2] IRQ_MUX[3] DREQ_MUX[0] DREQ_MUX[1] DACK_ENC[0] DACK_ENC[1] DACK_ENC[2] TC KBCS# PIRQ SIRQ PDRQ SDRQ PDACK# Pin # D1 E2 E4 E3 E1 AF9 AE9 AD8 AC5 AE5 AC10 AE10 AD7 AF8 AD9 AC9 AF10 AE15 AD5 AF7 AF5 AE6 AC7 AD6 AF6 AE7 AD10 AF11 AE12 AF14 AE11 AF12 AE14 AC14 AD12 AE13 AC12 AF13 C5 B5 C7 B3 G24 AD13 Pin name SDACK# PDIOR# PDIOW# SDIOR# SDIOW# RED GREEN BLUE VSYNC HSYNC VREF_DAC RSET COMP VDD_DAC1 VDD_DAC2 VSS_DAC1 VSS_DAC2 VCLK VIN[0] VIN[1] VIN[2] VIN[3] VIN[4] VIN[5] VIN[6] VIN[7] RED_TV GREEN_TV BLUE_TV CVBS IREF1_TV VREF1_TV IREF2_TV VREF2_TV VDDA_TV VCS ODD_EVEN VSSA_TV SPKRD SCL SDA SCAN_ENABLE VDD_CPUCLK_PLL VDD_DCLK_PLL Issue 1.1 - October 16, 2000 21/59 PIN DESCRIPTION Pin # F25 AC17 AC15 F26 A16 B11 B9 D18 D6 D11 D16 D21 F4 F23 L4 L23 T4 T23 AA4 AA23 AC6 AC11 AC16 AC21 E25 E26 A1:2 A26 B2 B25:26 C3 C24 D4 D9 D14 D19 D23 H4 J23 L11:16 M11:16 N4 N11:16 P11:16 P23 R11:16 T11:16 V4 Pin name VDD_DEVCLK_PLL VDD_MCLKI_PLL VDD_MCLKO_PLL VDD_HCLK_PLL VDD5 VDD5 VDD5 VDD5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS_DLL VSS_DLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin # W23 AC4 AC8 AC13 AC18 AC23 AD3 AD14 AD24 AE1:2 AE25 AF1 AF25 AF26 A20 C15 G3 G26 N1 W1 AC2 Pin name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected Unconnected 22/59 Issue 1.1 - October 16, 2000 STRAP OPTIONS 3 STRAP OPTIONS This chapter defines the STPC Consumer-S Strap Options and their location Memory Data Lines MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 Actual Settings Refer to ISA Control PCI Clock Host Clock Memory Clock Dot Clock HCLK Designation Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Master# PCI_CLKO Divisor HCLK Pad Direction MCLK Pad Direction DCLK Pad Direction Reserved Reserved Reserved HCLK PLL Speed Location Index 4A, bit 0 Index 4A, bit 1 Index 4A, bit 2 Index 4A, bit 3 Index 4A, bit 4 Index 4A, bit 5 Index 4A, bit 6 Index 4A, bit 7 Index 4B, bit 0 Index 4B, bit 1 Index 4B, bit 2 Index 4B, bit 3 Index 4B, bit 4 Index 4B, bit 5 Index 4B, bit 6 Index 4B, bit 7 Index 4C,bit0 Index 4C,bit 1 Index 4C,bit 2 Index 4C,bit 3 Index 4C, bit4 Index 5F, bit 0 Index 5F, bit 1 Index 5F,bit 2 Index 5F,bit 3 Index 5F,bit 4 Index 5F,bit 5 Set to '0' Set to '1' User defined Test mode Normal User defined HCLK / 3 HCLK / 2 User defined External Internal User defined External Internal User defined External Internal Pull up Pull up Pull up User defined 000 25 MHz User defined 001 33 MHz User defined 010 100 MHz 011 50 MHz 100 60 MHz 101 66 MHz 110 75 MHz 111 90 MHz Hardware Pull down MD27 Reserved Hardware Pull down MD28 Reserved Hardware Pull down MD29 Reserved Hardware Pull down MD30 REserved Reserved Hardware Pull down MD31 Reserved Hardware Pull down MD32 Reserved Hardware Pull down MD33 Reserved Hardware Pull down MD34 Reserved Hardware Pull down MD35 Note; Where the indication hardware appears, the strap options are selected directly on the board by jumpers or resistances. Refer to the reference schematics for examples. Issue 1.1 - October 16, 2000 23/59 STRAP OPTIONS Memory Actual Data Refer to Designation Location Set to '0' Set to '1' Settings Lines MD36 Reserved MD37 Reserved MD38 Reserved MD39 Reserved MD40 CPU CPU Mode Hardware User defined DX1 DX2 MD41 Reserved Hardware Pull down MD42 Reserved Hardware Pull up MD43 Reserved Hardware Pull down Reserved MD44 Hardware Pull down Reserved MD45 Hardware Pull up Reserved MD46 Hardware Pull down MD47 Reserved Hardware Pull down Reserved MD48 Hardware Pull up Note; Where the indication hardware appears, the strap options are selected directly on the board by jumpers or resistances. Refer to the reference schematics for examples. 3.1 Power on strap registers description 3.1.1 Strap register 0 Configuration Index 4Ah (Strap0) 1: Internal. MCLKO pin is an output and is connected to the internal frequency synthesizer output. Bit 2 This bit reflects the value sampled on MD[18] pin and controls the Host/CPU clock source as follows: 0: External. HCLK pin is an input. 1: Internal. HCLK pin is an output and is connected to the internal frequency synthesizer output. Bit 1 This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows: 0: PCI clock output = HCLK / 3 1: PCI clock output = HCLK / 2 Bit 0 This bit reflects the value sampled on MD[16] pin and controls the configuration of MASTERx and either SD[15:8] (in user mode) or VIN[7:0] for use in test/debug modes. 0: Configured as test bus. 1: Configured as normal IOs. This register defaults to the values sampled on MD[23] & MD[20:16] pins after reset. This register is Reserved. 3.1.2 Strap register 1 Configuration Index 4Bh (Strap1) This register is Reserved. 3.1.3 Strap register 2 Configuration Index 4Ch (Strap2) Bits 7-5 Reserved. Bit 4 This bit reflects the value sampled on MD[20] pin and controls the Dot clock (DCLK) source as follows: 0: External. DCLK pin is an input. 1: Internal. DCLK pin is an output and is connected to the internal frequency synthesizer output. Note this bit is writeable as well as readable. Bit 3 This bit reflects the value sampled on MD[19] pin and controls the Memory clock output (MCLKO) source as follows: 0: External. MCLKO pin is tristated. 24/59 Issue 1.1 - October 16, 2000 STRAP OPTIONS 3.1.4 HCLK Strap register Configuration Index 5Fh (HCLK_Strap) Bits 7-6 Reserved. Bits 5-3 These pins reflect the value sampled on MD[26:24] pins respectively and control the Host clock frequency synthesizer as follows: Bit 5 0 0 0 0 1 1 1 1 Bit 4 0 0 1 1 0 0 1 1 Bit 3 0 1 0 1 0 1 0 1 Description 25 MHz 33 MHz 100 MHz 50 MHz 60 MHz 66 MHz 75 MHz 90 MHz grammed through strap values on MD[35:31] & MD[46:45]. MD[46:45] set the source of the HCLKI and the programming value if the PLL option is chosen. MD[46:45] HCLKI source MD[46] MD[45] HCLKI Source HCLKI PLL enabled & HCLKI frequen0 0 cy between 16 & 32 MHz HCLKI PLL enabled & HCLKI frequen0 1 cy between 32 & 64 MHz HCLKI PLL enabled & HCLKI frequen1 0 cy greater than 64 MHz HCLKI PLL disabled; delay chains se1 1 lected Bit 2-0 Reserved. This register defaults to the values sampled on above pins after reset. The recommended value for these three bits is 110. 3.1.5 Delay Programming For DLL (DLL_Prog) The bits MD[30:27] are used to set the delay of the host clock entering the on chip DLL used to generate PCI_CLKO that is synchronous with HCLK. Please refer to the STPC Consumer-S Reference Design Schematics for the appropriate value or contact your ST application engineer. 3.1.6 HCLKI Programming (HCLK_Prog) The HCLKI clock signal (the clock that is used in the ADPC std cell logic) is selected and pro- CPU to HCLKI skew, MD[35:31] are used to set the correct skew between the HCLKI and the CPU clock. MD[35] controls whether the CPU clock leads (strap to vss) or lags (strap to vdd) the chipset host clock. MD[34:31] set the value of the skew between these two clocks. Contact your ST applications support for the correct value to strap to these bits. These bits are only enabled when MD[46:45] == 11. 3.1.7 486 Clock Programming (486_Prog) The bit MD[40] is used to set the clock multiplication factor of the 486 core. With the MD[40] pin pulled low the 486 will run in DX (x1) mode, while with the MD[40] pin pulled high the 486 will run in DX2 (x2) mode. The default value of the resistor on this strap input should be a resister to gnd (DX mode). CPU clock tic, MD[43:41] are used to set the clock tic input value for the 486 core DLL. The recommended value for these three bits is 010. Issue 1.1 - October 16, 2000 25/59 ELECTRICAL SPECIFICATIONS 4 ELECTRICAL SPECIFICATIONS 4.1 Introduction The electrical specifications in this chapter are valid for the STPC Consumer-S. 4.2 Electrical Connections 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Consumer-S, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the STPC Consumer-S and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VSS and VDD pins. 4.2.2 Unused Input Pins All inputs not used by the designer and not listed in the table of pin connections in Chapter 3 should be connected either to VDD or to VSS. Connect active-high inputs to VDD through a 20 k (10%) pull-down resistor and active-low inputs to VSS and connect active-low inputs to VCC through a Table 4-1. Absolute Maximum Ratings Symbol Parameter VDDx DC Supply Voltage VI, VO Digital Input and Output Voltage TSTG Storage Temperature PTOT Total Power Dissipation (HCLK = 90MHz, MCLK = 75MHz) Note 1; See Table 5.2 for heat dissipation requirements Value -0.3, 4.0 -0.3, VDD + 0.3 -40, +150 4.91 Units V V C W 20 k (10%) pull-up resistor to prevent spurious operation. 4.2.3 Reserved Designated Pins Pins designated reserved should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 Absolute Maximum Ratings The following table lists the absolute maximum ratings for the STPC Consumer-S device. Stresses beyond those listed under Table 4-1 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those specified in section "Operating Conditions". Exposure to conditions beyond Table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 4-1) may also result in reduced useful life and reliability. 26/59 Issue 1.1 - October 16, 2000 ELECTRICAL SPECIFICATIONS 4.4 DC Characteristics Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.45V 0.15V, Tcase = 0 to 100C unless otherwise specified Symbol Parameter VDD Operating Voltage PDD Supply Power HCLK VREF VOL VOH VIL VIH ILK Idd CIN COUT CCLK Internal Clock DAC Voltage Reference Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Leakage Current Dynamic Current Input Capacitance Output Capacitance Clock Capacitance Test conditions VDD=3.45V, HCLK=75Mhz, MCLK=75MHz VDD=3.45V, HCLK=90Mhz, MCLK=75MHz Min 3.3 Typ 3.45 4.5 4.6 1.12 (Note 1) 1.04 I Load =1.5 to 8mA depending of the pin ILoad =-0.5 to -8mA depending of the pin Except XTALI XTALI Except XTALI XTALI Input, I/O at RESET, HCLK = 66Mhz, VDD = 3.45V, @Room Temp (Note 2) (Note 2) (Note 2) 2.4 -0.3 -0.3 2.1 2.35 -5 1.8 Unit V W W Mhz V V V 0.8 V 0.9 V VDD+0.15 V VDD+0.15 V 5 A A pF pF pF Max 3.6 4.7 4.9 75 1.20 0.5 Notes: 1. MHz ratings refer to CPU clock frequency. 2. Not 100% tested. 4.5 AC Characteristics Table 4-4 through Table 4-9 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1. The rising clock edge reference level VREF , and other reference levels are shown in Table 4-3 below for the STPC Consumer-S. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation. Table 4-3. Drive Level and Measurement Points for Switching Characteristics Symbol VREF VIHD VILD Value 1.5 3.0 0.0 Units V V V Note: Refer to Figure 4-1. Issue 1.1 - October 16, 2000 27/59 ELECTRICAL SPECIFICATIONS Figure 4-1. Drive Level and Measurement Points for Switching Characteristics Tx VIHD CLK: A B MIN VRef Valid Output n+1 MAX VRef VILD OUTPUTS: Valid Output n C D VIHD Valid Input INPUTS: VRef VILD LEGEND: A B C D - Maximum Output Delay Specification - Minimum Output Delay Specification - Minimum Input Setup Specification - Minimum Input Hold Specification 28/59 Issue 1.1 - October 16, 2000 ELECTRICAL SPECIFICATIONS 4.5.1 POWER ON SEQUENCE 3 .4 5 V S u p ply 1 4M H z > 1 0 us S Y S R S T I# 1 .6 V S tra p O p tio ns V A L ID C O N F IG U R A T IO N HCLK P C I_ C L K SYSRSTO# 2 .3 m s FRAM E# SYSRSTI# has no constraint on its rising time but needs to be set to high at least 10s after power supply is stable. Strap Options are continuously sampled during SYSRSTI# low and should be stable. Once SYSRSTI# is high, they MUST NOT CHANGE until SYSRSTO# is high. Issue 1.1 - October 16, 2000 29/59 ELECTRICAL SPECIFICATIONS Table 4-4. PCI Bus AC Timing Name t1 t2 t3 t4 t5 T6 Parameter PCI_CLKI to any output Setup to PCICKLI Hold from PCICLKI PCICLKI to PCI_GNT# output valid PCI_REQ# setup to PCI_CLKI PCI_REQ# hold to PCI_CLKI Min 7.0 1.0 12.0 0.0 Max 12.8 12.0 Unit ns ns ns ns ns ns Table 4-5. IDE Bus AC Timing Name t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 Parameter PCI_CLKI to SA[19:8] Active PCI_CLKI to RMRTCCS# Active PCI_CLKI to KBCS# Active PCI_CLKI to RTCRW# Active PCI_CLKI to RTCDS Active SA[19:8] Input Setup to SIOR# Rising SA[19:8] Input Hold to SIOR# Rising RMRTCCS# Input Setup to SIOR# Rising RMRTCCS# Input Hold to SIOR# Rising KBCS# Input Setup to SIOR# Rising KBCS# Input Hold to SIOR# Rising RTCRW# Input Setup to SIOR# Rising RTCRW# Input Hold to SIOR# Rising RTCDS Input Setup to SIOR# Rising RTCDS Input Hold to SIOR# Rising PCI_CLKI to LA[23:17] Active PCI_CLKI to PDACK# Active PCI_CLKI to SDACK Active PCI_CLKI to PIOR# Active PCI_CLKI to PIOW# Active PCI_CLKI to SIOR# Active PCI_CLKI to SIOW# Active Min -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 Max 42 42 42 42 42 10 10 10 10 10 10 10 10 10 10 28 32 32 28 28 28 28 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 4-6. SDRAM Bus AC Timing Name Parameter Min Max t42 MCLKI to RAS#[1:0] Output Valid 6.2 t43 MCLKI to CAS#[1:0] Output Valid 6.2 t44 MCLKI to CS#[3:0] Output Valid 7.6 t45 MCLKI to DQM#[7:0] Output Valid 8.1 Note; The figures are extrapolated from silicon characterisation results and design timing analysis Please refer to STPC Consumer-S Programming Manual for RDCLK settings Unit ns ns ns ns 30/59 Issue 1.1 - October 16, 2000 ELECTRICAL SPECIFICATIONS Table 4-6. SDRAM Bus AC Timing Name Parameter Min Max t46 MCLKI to MA[11:0] Output Valid 6.2 t47 MCLKI to MWE# Output Valid 6.2 t48 MCLKI to MD[63:0] Output Valid 8.2 t49 MD[63:0] setup to MCKLI (no RDCLK) 8.2 t50 MD[63:0] setup to MCKLI (RDCLK at min delay) 4.9 t51 MD[63:0] setup to MCKLI (RDCLK at mid delay) 4.0 t52 MD[63:0] setup to MCKLI (RDCLK at max delay) 3.0 t53 MD[63:0] hold from MCKLI (no RDCLK) 3.1 t54 MD[63:0] hold from MCKLI (RDCLK at min delay) 6.5 t54 MD[63:0] hold from MCKLI (RDCLK at mid delay) 7.1 t55 MD[63:0] hold from MCKLI (RDCLK at max delay) 8.5 Note; The figures are extrapolated from silicon characterisation results and design timing analysis Please refer to STPC Consumer-S Programming Manual for RDCLK settings Unit ns ns ns ns ns ns ns ns ns ns ns Table 4-7. Video Input/TV Output AC Timing Name t56 t57 t58 t59 t60 t61 t62 t63 Parameter VIN[7:0] setup to VCLK VIN[7:0] hold from VCLK VCLK to ODD_EVEN valid VCLK to VCS valid ODD_EVEN setup to VCLK ODD_EVEN hold from VCLK VCS setup to VCLK VCS hold from VCLK Min 5 4 Max Unit ns ns ns ns ns ns ns ns 15 15 10 5 10 5 Table 4-8. Graphics Adapter (VGA) AC Timing Name t64 t65 Parameter DCLK to VSYNC valid DCLK to HSYNC valid Min Max 30 30 Unit ns ns Issue 1.1 - October 16, 2000 31/59 ELECTRICAL SPECIFICATIONS Figure 4-2 ISA Cycle (ref table Table 4-9) 2 15 38 37 14 13 12 9 18 ALE 22 AEN Valid AENx 34 33 LA [23:17] 3 Valid Address 42 11 24 41 10 SA [19:0] Valid Address, SBHE* 26 23 55 48 47 61 CONTROL (Note 1) IOCS16# MCS16# 54 IOCHRDY READ DATA WRITE DATA VALID DATA V.Data 64 58 59 28 57 27 25 56 29 Note 1; Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#. Note; The clock has not been represented as it cannot be accuratly represented depending on the ISA Slave mode. Table 4-9. ISA Bus AC Timing Parameter LA[23:17] valid before ALE# negated LA[23:17] valid before MEMR#, MEMW# asserted 3a4 Memory access to 16 bit ISA Slave 3b4 Memory access to 8 bit ISA Slave 4 9 SA[19:0] & SBHE valid before ALE# negated SA[19:0] & SBHE valid before MEMR#, MEMW# asserted 104 10a4 Memory access to 16 bit ISA Slave 10b4 Memory access to 8 bit ISA Slave 4 10 SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted 10c4 Memory access to 16 bit ISA Slave 10d4 Memory access to 8 bit ISA Slave 4 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted XTALO to IOW# valid 114 11a4 Memory access to 16 bit ISA Slave - 2BCLK 11b4 Memory access to 16 bit ISA Slave - Standard 3BCLK Note; The signal numbering refers to Table 4-2 Name 24 34 Min 5T 5T 5T 1T 2T 2T 2T 2T 2T 2T 2T Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycle Cycle Cycles Cycles Cycles Note 4; These timings are extracted from simulations and are not garanteed by testing 32/59 Issue 1.1 - October 16, 2000 ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Parameter Min 11c4 Memory access to 16 bit ISA Slave - 4BCLK 2T 11d4 Memory access to 8 bit ISA Slave - 2BCLK 2T 11e4 Memory access to 8 bit ISA Slave - Standard 3BCLK 2T 4 12 ALE# asserted before ALE# negated 1T 134 ALE# asserted before MEMR#, MEMW# asserted 13a4 Memory Access to 16 bit ISA Slave 2T 13b4 Memory Access to 8 bit ISA Slave 2T ALE# asserted before SMEMR#, SMEMW# asserted 134 13c4 Memory Access to 16 bit ISA Slave 2T 13d4 Memory Access to 8 bit ISA Slave 2T 13e4 ALE# asserted before IOR#, IOW# asserted 2T ALE# asserted before AL[23:17] 144 14a4 Non compressed 15T 14b4 Compressed 15T ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated 154 15a4 Memory Access to 16 bit ISA Slave- 4 BCLK 11T 15e4 Memory Access to 8 bit ISA Slave- Standard Cycle 11T 18a4 ALE# negated before LA[23:17] invalid (non compressed) 14T 18a4 ALE# negated before LA[23:17] invalid (compressed) 14T MEMR#, MEMW# asserted before LA[23:17] 224 22a4 Memory access to 16 bit ISA Slave. 13T 22b4 Memory access to 8 bit ISA Slave. 13T MEMR#, MEMW# asserted before MEMR#, MEMW# negated 234 23b4 Memory access to 16 bit ISA Slave Standard cycle 9T 23e4 Memory access to 8 bit ISA Slave Standard cycle 9T SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated 234 23h4 Memory access to 16 bit ISA Slave Standard cycle 9T 23l4 Memory access to 16 bit ISA Slave Standard cycle 9T 234 IOR#, IOW# asserted before IOR#, IOW# negated 23o4 Memory access to 16 bit ISA Slave Standard cycle 9T 23r4 Memory access to 8 bit ISA Slave Standard cycle 9T MEMR#, MEMW# asserted before SA[19:0] 244 24b4 Memory access to 16 bit ISA Slave Standard cycle 10T 24d4 Memory access to 8 bit ISA Slave - 3BLCK 10T 24e4 Memory access to 8 bit ISA Slave Standard cycle 10T 24f4 Memory access to 8 bit ISA Slave - 7BCLK 10T SMEMR#, SMEMW# asserted before SA[19:0] 244 24h Memory access to 16 bit ISA Slave Standard cycle 10T 24i4 Memory access to 16 bit ISA Slave - 4BCLK 10T 24k4 Memory access to 8 bit ISA Slave - 3BCLK 10T 24l4 Memory access to 8 bit ISA Slave Standard cycle 10T IOR#, IOW# asserted before SA[19:0] 244 24o4 I/O access to 16 bit ISA Slave Standard cycle 19T 24r4 I/O access to 16 bit ISA Slave Standard cycle 19T MEMR#, MEMW# asserted before next ALE# asserted 254 Note; The signal numbering refers to Table 4-2 Note 4; These timings are extracted from simulations and are not garanteed by testing Name Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 1.1 - October 16, 2000 33/59 ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Parameter Min 25b4 Memory access to 16 bit ISA Slave Standard cycle 10T 25d4 Memory access to 8 bit ISA Slave Standard cycle 10T SMEMR#, SMEMW# asserted before next ALE# aserted 254 25e4 Memory access to 16 bit ISA Slave - 2BCLK 10T 25f4 Memory access to 16 bit ISA Slave Standard cycle 10T 25h4 Memory access to 8 bit ISA Slave Standard cycle 10T IOR#, IOW# asserted before next ALE# asserted 254 25i4 I/O access to 16 bit ISA Slave Standard cycle 10T 25k4 I/O access to 16 bit ISA Slave Standard cycle 10T MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted 264 26b4 Memory access to 16 bit ISA Slave Standard cycle 12T 26d4 Memory access to 8 bit ISA Slave Standard cycle 12T SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted 264 26f4 Memory access to 16 bit ISA Slave Standard cycle 12T 26h4 Memory access to 8 bit ISA Slave Standard cycle 12T IOR#, IOW# asserted before next IOR#, IOW# asserted 264 I/O access to 16 bit ISA Slave Standard cycle 12T 26i4 26k4 I/O access to 8 bit ISA Slave Standard cycle 12T Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted 284 28a4 Memory access to 16 bit ISA Slave 3T 28b4 Memory access to 8 bit ISA Slave 3T Any command negated to IOR#, IOW# asserted 284 28c4 I/O access to ISA Slave 3T 4 29a MEMR#, MEMW# negated before next ALE# asserted 1T 29b4 SMEMR#, SMEMW# negated before next ALE# asserted 1T 29c4 IOR#, IOW# negated before next ALE# asserted 1T LA[23:17] valid to IOCHRDY negated 334 33a4 Memory access to 16 bit ISA Slave - 4 BCLK 8T 33b4 Memory access to 8 bit ISA Slave - 7 BCLK 14T LA[23:17] valid to read data valid 344 34b4 Memory access to 16 bit ISA Slave Standard cycle 8T 34e4 Memory access to 8 bit ISA Slave Standard cycle 14T ALE# asserted to IOCHRDY# negated 374 37a4 Memory access to 16 bit ISA Slave - 4 BCLK 6T 37b4 Memory access to 8 bit ISA Slave - 7 BCLK 12T 37c4 I/O access to 16 bit ISA Slave - 4 BCLK 6T 37d4 I/O access to 8 bit ISA Slave - 7 BCLK 12T ALE# asserted to read data valid 384 38b4 Memory access to 16 bit ISA Slave Standard Cycle 4T 4 38e Memory access to 8 bit ISA Slave Standard Cycle 10T 38h4 I/O access to 16 bit ISA Slave Standard Cycle 4T 38l4 I/O access to 8 bit ISA Slave Standard Cycle 10T SA[19:0] SBHE valid to IOCHRDY negated 414 41a4 Memory access to 16 bit ISA Slave 6T 41b4 Memory access to 8 bit ISA Slave 12T Note; The signal numbering refers to Table 4-2 Note 4; These timings are extracted from simulations and are not garanteed by testing Name Max Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles 34/59 Issue 1.1 - October 16, 2000 ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Parameter Min Max 41c4 I/O access to 16 bit ISA Slave 6T 41d4 I/O access to 8 bit ISA Slave 12T 4 SA[19:0] SBHE valid to read data valid 42 42b4 Memory access to 16 bit ISA Slave Standard cycle 4T 42e4 Memory access to 8 bit ISA Slave Standard cycle 10T 42h4 I/O access to 16 bit ISA Slave Standard cycle 4T 42l4 I/O access to 8 bit ISA Slave Standard cycle 10T MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated 474 47a4 Memory access to 16 bit ISA Slave 2T 47b4 Memory access to 8 bit ISA Slave 5T 47c4 I/O access to 16 bit ISA Slave 2T 47d4 I/O access to 8 bit ISA Slave 5T MEMR#, SMEMR#, IOR# asserted to read data valid 484 48b4 Memory access to 16 bit ISA Slave Standard Cycle 2T 48e4 Memory access to 8 bit ISA Slave Standard Cycle 5T 48h4 I/O access to 16 bit ISA Slave Standard Cycle 2T 48l4 I/O access to 8 bit ISA Slave Standard Cycle 5T IOCHRDY asserted to read data valid 544 54a4 Memory access to 16 bit ISA Slave 1T(R)/2T(W) 54b4 Memory access to 8 bit ISA Slave 1T(R)/2T(W) 54c4 I/O access to 16 bit ISA Slave 1T(R)/2T(W) 54d4 I/O access to 8 bit ISA Slave 1T(R)/2T(W) IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, 1T 55a4 SMEMW#, IOR#, IOW# negated 4 IOCHRY asserted to MEMR#, SMEMR# negated (refresh) 1T 55b 564 IOCHRDY asserted to next ALE# asserted 2T 574 IOCHRDY asserted to SA[19:0], SBHE invalid 2T 4 58 MEMR#, IOR#, SMEMR# negated to read data invalid 0T 594 MEMR#, IOR#, SMEMR# negated to daabus float 0T 614 Write data before MEMW# asserted 61a4 Memory access to 16 bit ISA Slave 2T Memory access to 8 bit ISA Slave (Byte copy at end of 2T 61b4 start) Write data before SMEMW# asserted 614 61c4 Memory access to 16 bit ISA Slave 2T 61d4 Memory access to 8 bit ISA Slave 2T Write Data valid before IOW# asserted 614 61e4 I/O access to 16 bit ISA Slave 2T 61f4 I/O access to 8 bit ISA Slave 2T 4 64a MEMW# negated to write data invalid - 16 bit 1T 64b4 MEMW# negated to write data invalid - 8 bit 1T 64c4 SMEMW# negated to write data invalid - 16 bit 1T 64d4 SMEMW# negated to write data invalid - 8 bit 1T 64e4 IOW# negated to write data invalid 1T Note; The signal numbering refers to Table 4-2 Note 4; These timings are extracted from simulations and are not garanteed by testing Name Units Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Cycles Issue 1.1 - October 16, 2000 35/59 ELECTRICAL SPECIFICATIONS Table 4-9. ISA Bus AC Timing Parameter MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte by ISA Master IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by 64g4 ISA Master Note; The signal numbering refers to Table 4-2 64f4 Name Min 1T 1T Max Units Cycles Cycles Note 4; These timings are extracted from simulations and are not garanteed by testing 36/59 Issue 1.1 - October 16, 2000 MECHANICAL DATA 5. MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View Dimensions are shown in Figure 5-2, Table 5-1 and Figure 5-3, Table 5-2. 1 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Issue 1.1 - October 16, 2000 37/59 MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A B A E F D Detail CG Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols A B C D E F G Min 34.95 1.22 0.58 1.57 0.15 0.05 0.75 mm Typ 35.00 1.27 0.63 1.62 0.20 0.10 0.80 Max 35.05 1.32 0.68 1.67 0.25 0.15 0.85 Min 1.375 0.048 0.023 0.062 0.006 0.002 0.030 inches Typ 1.378 0.050 0.025 0.064 0.008 0.004 0.032 Max 1.380 0.052 0.027 0.066 0.001 0.006 0.034 38/59 Issue 1.1 - October 16, 2000 MECHANICAL DATA Figure 5-3. 388-pin PBGA Package - Dimensions C F D E Solderball Solderball after collapse B A G Table 5-2. 388-pin PBGA Package - Dimensions Symbols A B C D E F G Min 0.50 1.12 0.60 0.52 0.63 0.60 mm Typ 0.56 1.17 0.76 0.53 0.78 0.63 30.0 Max 0.62 1.22 0.92 0.54 0.93 0.66 Min 0.020 0.044 0.024 0.020 0.025 0.024 inches Typ 0.022 0.046 0.030 0.021 0.031 0.025 11.8 Max 0.024 0.048 0.036 0.022 0.037 0.026 Issue 1.1 - October 16, 2000 39/59 MECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Structure in shown in Figure 5-4. Thermal dissipation options are illustrated in Figure 5-5 and Figure 5-6. Signal layers Power & Ground layers Thermal balls Figure 5-5. Thermal dissipation without heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 6 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 125 The PBGA is centered on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the center balls Ambient Rja = 13 C/W 40/59 Issue 1.1 - October 16, 2000 MECHANICAL DATA Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Board 8.5 3 Junction Board dimensions: - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 GND, 1VCC) 6 Case 50 The PBGA is centered on board There are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers Copper thickness: - 17m for internal layers - 34m for external layers Airflow = 0 Board temperature taken at the center balls Heat sink is 11.1C/W Ambient Rja = 9.5 C/W Issue 1.1 - October 16, 2000 41/59 BOARD LAYOUT 6. BOARD LAYOUT 6.1 Thermal dissipation Thermal dissipation of the STPC depends mainly on supply voltage. As a result, when the system does not need to work at 3.45V, it is interesting to reduce the voltage to 3.15V, for example, if it is possible. This may save few 100's of mW. The second area to look at is unused interfaces and functions. Depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. Clock speed dynamic adjustment is also a solution that can be used along with the integrated power management unit. The standard way to route thermal balls to internal ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. Figure 6-1. Ground routing With such configuration the Plastic BGA 388 package does 90% of the thermal dissipation through the ground balls, and especially the central thermal balls which are directly connected to the die, the remaining 10% is dissipated through the case. Adding a heat sink reduces this value to 85%. As a result, some basic rules has to be applied when routing the STPC in order to avoid thermal problems. First of all, the whole ground layer acts as a heat sink and ground balls must be directly connected to it as illustrated in Figure 6-1. If one ground layer is not enough, a second ground plane may be added on solder side. Pad for ground ball Thru hole to ground layer To pL aye r: Sig na Gro ls un d la yer Po we r la yer Bo tto m La yer : si gn als + lo cal gro un d la yer (if ne ed ed ) Note: For better visibility, ground balls are not all routed. 42/59 Issue 1.1 - October 16, 2000 BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The use of a 8-mil wire results in a thermal resistance of 105C/W assuming copper is used (418 W/ m.K). This high value is due to the thickness (34 m) of the copper on the external side of the PCB. Considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9C/W. This can be easily improved using four 10 mil wires to connect to the four vias around the ground pad link as in Figure 6-3. This gives a total of 49 vias and a global resistance for the 36 thermal balls of 0.6C/W. The use of a ground plane like in Figure 6-4 is even better. To avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (NSMD pad), this gives a diameter of 33 mil for a 25 mil ground pad. To obtain the optimum ground layout, place the vias directly under the ball pads. In this case no local boar d distortion is tolerated. The thickness of the copper on PCB layers is typically 34 m for external layers and 17 m for internal layers. That means thermal dissipation is not good and temperature of the board is concentrated around the devices and falls quickly with increased distance. When it is possible to place a metal layer inside the PCB, this improves dramatically the heat spreading and hence thermal dissipation of the board. Figure 6-2. Recommended 1-wire ground pad layout Pad for ground ball (diameter = 25 mil) Solder Mask (4 mil) Connection Wire (width = 10 mil) Via (diameter = 24 mil) Hole to ground layer (diameter = 12 mil) .5 34 Figure 6-3. Recommended 4-wire ground pad layout il m 1 mil = 0.0254 mm 4 via pads for each ground ball Issue 1.1 - October 16, 2000 43/59 BOARD LAYOUT Figure 6-4. Optimum layout for central ground ball Clearance = 6mil External diameter = 37 mil Via to Ground layer hole diameter = 14 mil Solder mask diameter = 33 mil Pad for ground ball diameter = 25 mil connections = 10 mil The PBGA Package dissipates also through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the peripheral ground balls. The more via pads are connected to each ground ball, the more heat is dissipated . The only limitation is the risk of lossing routing channels. Figure 6-5 shows a routing with a good trade off between thermal dissipation and number of routing channels. A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipation. It is used to connect decoupling capacitances but can also be used for connection to a heat sink or to the system's metal box for better dissipation. This possibility of using the whole system's box for thermal dissipation is very usefull in case of high temperature inside the system and low temperature outside. In that case, both sides of the PBGA should be thermally connected to the metal chassis in order to propagate the heat flow through the metal. Figure 6-7 illustrates such implementation. 6.2 High speed signals Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: 1) Memory Interface. 2) Graphics and video interfaces 3) PCI bus 4) 14MHz oscillator stage All the clocks haves to be routed first and shielded for speeds of 27MHz or more. The high speed signals follow the same contrainsts, like the memory control signals and the PCI control signals. The next interfaces to be routed are Memory, Video/graphics, and PCI. All the analog noise sensitive signals have to be routed in a separate area and hence can be routed indepedently. 44/59 Issue 1.1 - October 16, 2000 BOARD LAYOUT Figure 6-5. Global ground layout for good thermal dissipation Via to ground layer Ground pad Figure 6-6. Bottom side layout and decoupling Ground plane for thermal dissipation Via to ground layer Issue 1.1 - October 16, 2000 45/59 BOARD LAYOUT Figure 6-7. Use of metal plate for thermal dissipation Die Board Metal planes Figure 6-8. Shielding signals Thermal conductor ground ring shielded signal line ground pad ground pad shielded signal lines 46/59 Issue 1.1 - October 16, 2000 BOARD LAYOUT 6.3 Memory interface 6.3.1 Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 100MHz and above, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. The guidelines described below are related to SDRAM components on DIMM modules. For applications where the memories are directly soldered to the motherboard, the PCB should be laid out such that the trace lengths fit within the constraints shown here. The traces could be slightly longer since the extra routing on the DIMM PCB is Figure 6-9. Clock scheme no longer present but it is then up to the user to verify the timings. 6.3.2 SDRAM Clocking Scheme The SDRAM Clocking Scheme deserves a special mention here. Basically the memory clock is generated on-chip through a PLL and goes directly to the MCLKO output pin of the STPC. The nominal frequency is 100MHz. Because of the high load presented to the MCLK on the board by the DIMMs it is recommeded to rebuffer the MCLKO signal on the board and balance the skew to the clock ports of the different DIMMs and the MCLKI input pin of STPC. MCLKO PLL MCLKI DIMM2 DIMM1 PLL MA[] + Control register SDRAM CONTROLLER MD[] 6.3.3 Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown in Figure 6-10. Because all the memory interface signal balls are located in the same region of the STPC device it is possible to orientate the device to reduce the trace lengths. The worst case routing length to the DIMM1 is estimated to be 100mm. Solid power and ground planes are a must in order to provide good return paths for the signals and to reduce EMI and noise. Also there should be ample high frequency decoupling between the power and ground planes to provide a low impedance path between the planes for the return paths for signal routings which change layers. If possible the traces should be routed adjacent to the same power or ground plane for the length of the trace. For the SDRAM interface the most critical signal is the clock. Any skew between the clocks at the SDRAM components and the memory controller will impact the timing budget. In order to get well matched clocks at all the components it is recommended that all the DIMM clock pins, STPC memory clock input (MCLKI) and any other component using the memory clock are individually driven Issue 1.1 - October 16, 2000 47/59 BOARD LAYOUT Figure 6-10. DIMM placement 35mm STPC SDRAM I/F 35mm 15mm DIMM4 10mm DIMM3 DIMM2 DIMM1 116mm from a low skew clock driver with matched routing lengths. This is shown in Figure 6-11. Figure 6-11. Clock routing Low skew clock driver: L DIMM CKn input DIMM CKn input MCLKO DIMM CKn input L+75mm* STPC MCLKI 20pF * No additionnal 75mm when SDRAM directly soldered on board The maximum skew between pins for this part is 250ps. The important factors for the clock buffer are a consistent drive strength and low skew between the outputs. The delay through the buffer is not important so it does not have to be a zero delay PLL type buffer. The trace lengths from the clock driver to the DIMM CKn pins should be matched exactly. Since the propagation speed can vary between PCB layers the clocks should be routed in a consistent way. The routing to the 48/59 STPC memory input should be longer by 75mm to compensate for the extra clock routing on the DIMM. Also a 20pF capacitor should be placed as near as possible to the clock input of the STPC to compensate for the DIMM's higher clock load. The impedance of the trace used for the clock routing should be matched to the DIMM clock trace impedance (60-75 ohms). To minimise crosstalk the clocks should be routed with spacing to adjacent tracks of at least twice the clock trace width. Issue 1.1 - October 16, 2000 BOARD LAYOUT For designs which use SDRAMs directly mounted on the motherboard PCB all the clock trace lengths should be matched exactly. The DIMM sockets should be populated starting with the furthest DIMM from the STPC device first (DIMM1). There are 2 types of DIMM devices; single row and dual row. The dual row devices require 2 chip select signals to select between the two rows. A STPC device with 4 chip select control Figure 6-12. Optimum data bus layout for DIMM lines could control either 4 single row DIMMs or 2 dual row DIMMs. When using DIMM modules, schematics have to be done carefully in order to avoid data busses completely crossed on the board. This has to be checked at the library level. In order to achive layout shown in Figure 6-12, schematics have to implement the crossing described on Figure 6-13. The DQM signals must be exchanged using the same order. STPC MD[31:00] MD[63:32] SDRAM I/F D[15:00] D[47:32] D[31:16] D[63:48] DIMM Figure 6-13. Schematics for optimum data bus layout for DIMM STPC MD[15:00],DQM[1:0] MD[31:16],DQM[3:2] MD[47:32],DQM[5:4] MD[63:48],DQM[7:6] DIMM D[15:00],DQM[1:0] D[31:16],DQM[3:2] D[47:32],DQM[5:4] D[63:48],DQM[7:6] Issue 1.1 - October 16, 2000 49/59 BOARD LAYOUT 6.3.4 Address & Control Signals This group encompasses the memory address MA[10:0], bank address BA[0], RAS, CAS and write enable WE signals. The load of the DIMM module on these signals is the most important one and depends upon the type of SDRAM compoFigure 6-14. Address/control equivalent circuit nents used (x4, x8 or x16) and whether the DIMM module is single or dual row. The capacitive loading of the SDRAM inputs alone for an x8 single row DIMM will be about 30-40pF. An equivalent circuit for the timing simulation is shown in Figure 6-14 Most of the delays are due to the PCB traces and loading rather than the pad itself. DIMM3 DIMM4 Rterm 100mm (0.7ns) ZOpcb 10mm 50/59 Issue 1.1 - October 16, 2000 DIMM2 DIMM1 BOARD LAYOUT 6.3.5 Chip Select Signals (CS#[3:0]) There are 4 chip select pins per DIMM. Chip selects 0 and 2 are always used to select the first Figure 6-15. CS# equivalent circuit row of SDRAMs and chip selects 1 and 3 select the second row on dual bank SDRAMs. The chip select outputs only have to drive one DIMM each CS[2] Issue 1.1 - October 16, 2000 DIMM 130mm (0.9ns) CS[0] 51/59 BOARD LAYOUT 6.3.6 Data Write (MD[63:0]) The load on the data signals is much lower than the address/control signals for an unbuffered DIMM. For a registered DIMM the data signals are the only memory pins of the DIMM which are not registered. For the design to get maximum benefit from using registered DIMMs the timings should Figure 6-16. Data read equivalent circuit be compared to the timings for registered DIMMs for the other pins. 6.3.7 Data Read (MD[63:0]) The data read simulation circuit is shown below.. DIMM2 DIMM1 10 ohms SDRAM DQ DIMM3 DIMM4 125mm (0.9ns) 10mm 52/59 Issue 1.1 - October 16, 2000 BOARD LAYOUT 6.3.8 Data Mask (DQM[7:0]) The data mask load is quite similar to that of the data signals. 6.3.9 Summary For unbuffered DIMMs the address/control signals will be the most critical for timing. The simulations show that for these signals the best way to drive them is to use a parallel termination. For applications where speed is not so critical series termination can be used as this will save power. Using a low impedance such as 50 for these critical traces is recommended as it both reduces the delay and the overshoot. The other memory interface signals will typically be not as critical as the address/control signals for unbuffered DIMMs. When using registered DIMMs the other signals will probably be just as critical as the address/control signals so to gain maximum benefit from using registered DIMMs the timings should also be considered in that situation. Using lower impedance traces is also beneficial for the other signals but if their timing is not as critical as the address/control signals they could use the default value. Using a lower impedance implies using wider traces which may have an impact on the routing of the board. The following Figure 6-17 and Figure 6-18, shows two possible SDRAM organizations based on one or two bank configurations. Notes for Figure 6-17 and Figure 6-18; All buffers must be low skew clock buffers One clock driver can operate upto four memory chips. All the clock lines must follow the rules below; MCLKI = MCLK0 + MCLK0A = ...... = MCLK0 + MCLK0D = MCLK1 + MCLK1A = ...... = MCLK1 + MCLK1D This means that all line lengths must go from the buffer to the memory chips (MCLK1 or MCLK0 or ...) and from the buffer to the STPC (MCLKI) must be identical. 6.4 SDRAM LAYOUT EXAMPLES The STPC provides MA, RAS#, CAS#, WE#, CS#, DQM#, BA0 (MA[11])and MD for SDRAM control. From 2 to 128 MBytes of main memory are supported in 1 to 4 banks. All Banks must be 64 bits wide. The following memory devices are supported: 4Mbit x 4, 8Mbit x 2 & 16Mbit x 1 or if in the case of two internal bank chips, 2Mbit x 4 x 2, 4Mbit x 2 x 2 & 8Mbit x 1 x 2 . 6.4.1 Host Address to MA bus Mapping Graphics memory resides at the beginning of Bank 0. Host memory begins at the top of graphics memory and extends to the top of populated SDRAM. The bank attributes can be retrieved from a lookup table to select the final SDRAM row and column address mappings. (Table 6-2). Also Table 6-1 shows the Standard DIMM Pinout for the users that wish to design with DIMMs. . Issue 1.1 - October 16, 2000 53/59 54/59 Issue 1.1 - October 16, 2000 Figure 6-17. One memory Bank with eight chips (8-Bit) BOARD LAYOUT One Memory bank with eight devices (8-bit) MCLKI MCLKO Reference Knot (Each signal needs it's own line) MA[10:0] BA0 (MA[11]) CS0# WE# CAS# RAS# MCLK0A MCLK0B MCLK0C MCLK0D 16 MBit 16-bit wide 16 MBit 16-bit wide 16 MBit 16-bit wide 16 MBit 16-bit wide MD DQM [7:6] [63:48] DQM# DQM [5:4] MD [47:32] DQM [3:2] MD [31:16] DQM [1:0] MD [15:0] MD[63:0] BOARD LAYOUT MCLKI MCLKI MCKLO Clock Buffer Compulsary MCLK0/1 MCLK2/3 MCKLO Clock Buffer Compulsary MCLK4/5 MCLK6/7 Figure 6-18. Two memory banks with eight chips on each (8-Bit) (Each signal needs it's own line) MA[10:0] BA0 (MA[11]) MCLK0A CS0#,2#, WE# CAS#, RAS# MCLK0B MCLK1A MCLK1B MCLK2A MCLK2B MCLK3A MCLK3B 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide DQM [7] MD [63:56] DQM [6] MD [55:48] DQM [5] MD [47:40] DQM [4] MD [39:32] DQM [3] MD [31:24] DQM [2] MD [23:16] DQM [1] MD [15:8] DQM [0] MD [7:0] DQM# MD[63:0] Two Memory bank with eight devices (8-bit) (Each signal needs it's own line) MA[10:0] MCLK4A BA0 (MA[11]) CS1#,3#, WE# CAS#, RAS# MCLK4B MCLK5A MCLK5B MCLK6A MCLK6B MCLK7A MCLK7B 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide 16 MBit 8-bit wide DQM [7] MD [63:56] DQM [6] MD [55:48] DQM [5] MD [47:40] DQM [4] MD [39:32] DQM [3] MD [31:24] DQM [2] MD [23:16] DQM [1] MD [15:8] DQM [0] MD [7:0] DQM# MD[63:0] Issue 1.1 - October 16, 2000 55/59 BOARD LAYOUT Table 6-1. Standard Memory DIMM Pinout Memory Banks pin number ... 123 126 39 122 16Mbit(2 banks) MA[10:0] BA0(MA11) Table 6-2. Address Mapping Address Mapping: 16 Mbit - 2 STPC I/F BA0(MA11) RAS ADDRESS A11 CAS ADDRESS A11 banks MA10 MA9 A22 A21 0 A24 MA8 A2 A23 MA7 A19 A10 MA6 A18 A9 MA5 A17 A8 MA4 A16 A7 MA3 A15 A6 MA2 A14 A5 MA1 A13 A4 MA0 A12 A3 56/59 Issue 1.1 - October 16, 2000 ORDERING DATA 7 ORDERING DATA 7.1 Ordering Codes ST STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C03: Consumer-S Core Speed 66: 66MHz 75: 75MHz 90: 90MHz Package BT: 388 Overmoulded BGA Temperature Range PC C03 66 BT C 3 C: Commercial Case Temperature (Tcase) = 0C to +100C I: Industrial Case Temperature (Tcase) = -40C to +100C Operating Voltage 3 : 3.45V 0.3V Issue 1.1 - October 16, 2000 57/59 ORDERING DATA 7.2 Available Part Numbers Part Number STPCC0375BTC3 STPCC0390BTC3 Core Frequency ( MHz ) 75 90 CPU Mode ( X1 / X2 ) X1 X1 Tcase Range ( C ) 0C to +100 Operating Voltage (V) 3.45V 0.3V 58/59 Issue 1.1 - October 16, 2000 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 59 Issue 1.1 |
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